
Emulation Verification Engineer
- San Diego, CA
- Permanent
- Full-time
- Minimum BS and 10+ years relevant industry experience
- Experience with System Verilog, Verilog or UVM
- Experience in crafting test benches from scratch (Block and System Level)
- Experience in Regression Management and Triaging
- Experience with bring up, debugging and verification in Emulation
- Understanding of the tool flow from RTL to Emulation
- Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow
- Proven Design Verification or Silicon Validation skills
- Experience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertions
- Experience with System Verilog verification environments including C/C++ DPI, UVM
- Experience on any Scripting (Perl/Python/TCL)
- Excellent analytical and debug skills
- Hands on usage of Low Power methodologies (UPF based preferably)
- Experience in UVM Acceleration