Contributing to the development of new product opportunities by providing new competitive Digital IPs for our latest advanced DRAM. Have capability to come up design/verification requirements based on reference design and spec. Have capability to build high level algorithm behavior model for architecture verification. Could use RTL or custom way to design IPs and guide layout, verification team for final delivery. Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality BSEE or Greater, 6+ years of related experience Productive and efficient time usage thereby leading to more effective work. Satisfactory ability to convey or share ideas either verbally or in written form. Design high-preference digital circuits with STA compliance. RTL experience is preferred. Having an innovative approach that is open to improving upon any of our processes or products. Driving innovation into the future Memory generations within a dynamic work environment
