
ASIC Verification Engineer
- Santa Clara, CA
- Permanent
- Full-time
- Familiarity with UVM, System Verilog, and C or C++
- Basic experience with System Verilog simulators and waveform debuggers
- Exposure to developing and executing test plans for Unit/IP/Subsystem/SOC level verification
- Experience in System Verilog test bench development, including stimulus, checkers, transactors/BFMs, assertions, and cover points
- Ability to identify bugs in architecture, functionality, and performance, along with strong overall debug and analytical skills
- Exposure to design and verification tools such as VCS or equivalent simulation tools and debugging tools like Debussy/DVE
- Understanding of Computer Architecture concepts
- Strong analytical and problem-solving skills
- Excellent debugging capabilities
- Ability to work collaboratively in a team environment and communicate effectively with peers
BSEE or equivalent. MSEE preferredLOCATION:
Santa Clara, CA#LI-BW1#LI-hybridBenefits offered are described: .AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.