
Formal Design Verification Engineer
- Santa Clara, CA
- Permanent
- Full-time
- Lead formal verification team to ensure IP quality and project execution.
- Develop and implement comprehensive formal verification plans, including constraint/assertion property development, model development, inconclusive issue resolve and sign off, etc..
- Collaborate with IP architects, hardware designer, verification engineers, and other stakeholders to design efficient formal verification strategies.
- Mentor and guide junior engineers in formal verification techniques and best practices.
- Communicate results and progress effectively to cross-functional teams, providing insights and actionable recommendations.
- Drive continuous improvement in formal verification processes and contribute to the advancement of the organization's verification capabilities.
- Proven experience in formal verification and simulation, model checking, and theorem proving applied to complex IP or systems.
- Proficiency in formal verification tools such as VC-Formal or JasperGoal
- Strong understanding of hardware description languages (e.g., VHDL, Verilog) and/or programming languages (e.g., System verilog, C, C++, Python).
- Bachelors or Masters degree in computer engineering/Electrical Engineering