SoC Physical Design Engineer, PnR
Apple
- Austin, TX
- Permanent
- Full-time
- Minimum BS and 3+ years of relevant industry experience.
- Knowledgeable in partition level P&R implementation including floorplanning, clock and power distribution, timing closure, and physical and electrical verification.
- Strong knowledge of physical design construction and analysis flows and methodology.
- Shown ability to adhere to stringent schedule and die size requirements.
- Strong communication skills.
- Experienced with industry standard tools, understanding their capabilities and underlying algorithms.
- Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.
- Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. • Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. • Timing, physical and electrical verification, and driving the signoff closure for the partitions. • Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.