AI/GPU SoC Lead
- Hillsboro, OR
- Permanent
- Full-time
You will be responsible for working or assisting in architecture, implementation, formal verification, emulation and validation of AI GPU products, including:
- Lead a team of custom designers to produce key assets that help improve product KPI's for AI GPU products
- Working with SoC Architecture and platform architecture teams to establish silicon requirements
- Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule
- Creating micro architectural specification document for the design.
- Work with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.
- Drive vendor's methodology to meet world class silicon design standards
- Architecting area and power efficient low latency designs with scalabilities and flexibilities
- Power and Area efficient RTL logic design, and DV support
- Running tools to ensure lint-free and CDC/RDC clean design, VCLP
- Synthesis and timing constraints
- Having achieved multiple tape-outs reaching production with first pass silicon
- Ability to drive and improve digital design methodology to achieve high quality first silicon
- Hands on experience with FPGA emulation, silicon bring-up, characterization and debug
- Able to work with multi-functional teams and external vendors across geographical boundaries to resolve architectural and implementation challenges with an eye towards scheduling.
- Strong verbal and written communication skills
- Good understanding of verilog and system verilog, synthesizeable RTL
- Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis
- Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post silicon power correlation
- Background in computer architecture
- Bus fabric, including, but not limited to APB/AHB/AXI
- Power management with multiple power domains, UPF, Power state tables.
- Knowledge of lint tools, CDC and RDC tools, timing constraints, fishtail.
- Knowledge of connectivity tools.
- Understanding of key SoC design elements, arbiters, async FIFOs, DMAs, basic uControllers.
- Comprehension of asynchronous clock/reset crossing means and methodologies
- Proven track record of bringing logic designs into high volume production
- Ability to work well in a team and be productive under ambitious schedules
- Should be self-motivated and well organized