Perform Design Verification using UVM for complex module and system designs in Verilog. Work with architects and developers to agree on system requirements and implement test benches to verify that the modules and system meet requirements. Design system verification strategies to verify that the customer experience will meet expectations. Design, define and implement complex system requirements for customers or prepare studies and analyze existing systems. Coordinate design of subsystems and integration of total system. Develop and recommend corrective actions. Ensure maximum code coverage. Implement in Verilog and System Verilog. 1. Utilizing UVM for verification of complex module and system designs in Verilog; 2. Verilog and SystemVerilog; 3. Linux; 4. Software programming languages C++, Shell Scripting and Python; 5. Computer Architecture; 6. Synopsys/QuestaSim, Vivado Design Suite 7. Communication Protocols, including AXI and CPI; 8. GIT or Bitbucket software version management. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws. To learn about your right to work click here. AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
