Senior Staff Digital Design Engineer – Wireline PHYs
- Santa Clara, CA
- $124,420-186,400 per year
- Permanent
- Full-time
- Architect and implement RTL for digital control, DSP blocks, digital datapath, and adaptation engines of PHY IP targeting SerDes, Die-to-Die, and Parallel Optics applications.
- Design and verify bus interfaces (APB, AHB, AXI) and register maps for microcontroller communication and firmware control.
- Collaborate closely with system architects and firmware teams to optimize PHY integration into SoC and chiplet environments.
- Drive timing closure and ensure synthesis-friendly RTL targeting system-level constraints and goals, including DSP and datapath optimizations.
- Support system bring-up activities, validation planning, and post-silicon debug with a focus on system-level interactions involving digital datapath and DSP logic.
- Mentor junior engineers and contribute to improving design methodologies for PHY system integration, including DSP and datapath design best practices.
- Master’s degree +7 years or PhD +4 years in Electrical Engineering, Computer Engineering, or related fields.
- Strong RTL design expertise in Verilog/SystemVerilog, with a focus on digital control blocks, DSP, digital datapath, and bus protocols.
- Solid understanding of logic synthesis, static timing analysis (STA), constraints development, and timing closure at block and chip levels.
- Deep knowledge of CDC and RDC design principles.
- Experience integrating PHY digital blocks, including DSP and datapath modules, with embedded microcontrollers, including interrupt and event handling.
- Familiarity with scripting for design automation (Python, TCL, Perl).
- Proven problem-solving and debug experience at system level, including post-silicon validation, particularly for DSP and datapath components.
- Preferred: understanding of firmware-hardware co-design and system bring-up tools.