
ASIC Design Verification Engineer, Devices and Services
- Mountain View, CA
- Permanent
- Full-time
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 8 years of experience with verifying digital logic at RTL level using SystemVerilog or C/C++
- Experience creating and using verification components and environments in standard verification methodology
- Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems)
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture
- Experience with performance verification of SOCs, pre-Silicon analysis and post-Silicon correlation
- Experience with building verification methodologies that span simulation, emulation and FPGA prototypes
- Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL)
- Knowledge of scripting languages and software development frameworks
- Architectural background in one or more of the following: Low Power Design, Distributed Systems, DDR/LPDDR, PCIe, Processors and Memory Subsystems, Security, Clock and Power Controllers
- Plan and execute the verification of the next generation configurable infrastructure IPs, interconnects, and memory subsystems.
- Create and enhance constrained-random verification environments using SystemVerilog and UVM.
- Develop cross-language tools and scalable verification methodologies.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct blocks and subsystems, and close coverage measures to identify verification holes and to show progress towards tape-out.