
Principal DV Engineer - Memory Controller IP Development
- Hillsboro, OR
- Permanent
- Full-time
- Testbench and test sequence development for verification of new controller technologies and features
- Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage
- Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design
- Development & support of Verification environment scripting and capabilities
- Bachelors Degree or above in EE/CS, minimum 7 years experience with HDL logic Design-Verification
- System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must
- Pre-existing Experience / familiarity with DDR DRAM technology a strong preference
- Working experience with Python and TCL scripting languages preferred