Develop Physical Verification tools, flows, and methodologies for the next-generation DRAM, HBM, and Emerging memory designs. Collaborate closely with design, layout, verification, modeling, and process teams to resolve and implement product development and verification strategies. Evaluate EDA industry product offerings, ensuring we gain quality, performance, and efficiency in our processes. 10+ years of direct CAD or Physical Verification rule deck (DRC/LVS) development experience. Deep understanding and knowledge of physical verification methodologies, flows, and quality metrics. 5+ years of experience in CMOS circuit design, layout, and verification. 5+ years of experience with layout automation in Virtuoso using SKILL or Python. A bachelor's or master's degree or equivalent experience in Computer Science, Computer Engineering, Electrical Engineering, or Electronics Engineering. 1+ years of experience in developing and debugging Antenna/ESD/LUP checks. 1+ years of experience in DFM, tape-out, and Mask generation flows. 1+ years of experience with rule deck development using TVF or parasitic extraction. Outstanding communication and problem-solving skills. Ambitious aim to continuously learn, develop new skills, and self-improve!
