Remote - FPGA Engineer
The Hire Method
- Syracuse, NY
- $114,000-188,000 per year
- Permanent
- Full-time
- 3+ years of experience in FPGA design and development or related experience
- Proficiency in VHDL/Verilog and familiarity with FPGA toolchains (Xilinx, Intel, etc.)
- Proficiency with using Vivado or Quartus; knowledge of recent Xilinx/Intel FPGA architectures
- Proficiency using RTL simulation tools
- Deep understanding of digital logic design, embedded systems, and FPGA architecture
- Experience with FPGA debugging, timing analysis, and optimization techniques
- Must be eligible for a Secret Security clearance.
- Experience within the defense industry
- Current Secret Clearance (or higher)
- Architect, design and implement FPGA solutions using Very High-Speed Integrated Circuit Hardware Description Language (VHDL)/Verilog
- Design and optimize high-performance digital circuits and systems using VHDL/Verilog while adhering to industry best practices and digital design methodologies
- Conduct thorough functional and performance verification of FPGA designs through simulation and hardware testing, identifying, and resolving any design issues or bottlenecks
- Analyze and understand complex system requirements and translate them into efficient and optimized embedded architectures and designs
- Utilize advanced tools and techniques for FPGA implementation to achieve optimal performance, power, and area trade-offs
- Collaborate with digital board designers to ensure successful integration of FPGA designs onto PCBs and hardware platforms
- Stay up to date with the latest advancements in FPGA, SoC, RFSoC and other embedded technologies, tools, and methodologies
- Provide technical leadership and mentorship to junior engineers, fostering their growth and development in FPGA design
- Deep understanding of FPGA design flow including RTL design, verification, logic synthesis, prototyping, timing analysis, and lab debug
- Use Python, TCL and other scripting languages to automate continuous development, continuous integration (CI/CD) workflows