Develop test plans at SOC Level and analyze Coverage. Build verification environments to verify complex SOCs. Develop Random/Directed test in RTL and GLS environments. Review architectural specifications to ensure high quality. Work with customers to understand their verification and validation requirements and provide the necessary collateral. Engage with customers to support issues with current HBM architectures and find opportunities to innovate on future HBM solutions. Work with IP suppliers to ensure that proper verification and validation collaterals are provided. Be proactive in identifying and flagging quality issues, performance problems, and opportunities to reduce power consumption. Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products and architectures. BS in Electrical Engineering or a related equivalent field. At least 8 years of relevant experience in SoC/IP verification. 5+ years in writing tests and developing verification environments using SystemVerilog and UVM. 5+ years of experience with the writing assertions and coverage. Strong and relevant expertise with SoC simulation tools and advanced verification methods. MSEE or higher Proven track record of innovation and problem-solving in building verification environments and/or validating complex SOCs. 3+Years of semiconductor industry experience working with IP vendors and verifying IP integration. 3+ years working on gate-level simulation (GLS). 3+ years with scripting languages such as Python. Experience in any of the following IPs: UCIE, memory controller, NOCs, MBIST, ATPG scan controllers. Familiarity with DRAM operation and JEDEC specifications, preferably with the HBM product family. Good verbal and written communication skills with the ability to efficiently synthesize and convey sophisticated technical concepts to other partners and leadership.
