
SRAM Design Staff Engineer
- Austin, TX
- Permanent
- Full-time
- Technical lead for high speed SRAM design in deep submicron FinFET processes.
- Work closely with RTL and physical designers across multiple sites to optimize power, performance, area, and schedule.
- Solve design and tool problems requiring ground-breaking approaches and champion innovation across the organization. Create technical presentations for peers and management.
- Guide and mentor junior engineers.
- Hands-on experience in high speed SRAM design
- Excellent understanding of computer architecture, hardware concepts & design tradeoffs required
- Knowledge of Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, electromigration, Physical Verification and Sign Off.
- Comprehend complex Verilog RTL and make minor modifications for timing or power.
- Knowledge of digital circuits, high speed flops, synchronizers, level shifters, and SRAM.
- Familiar with programing languages such as Perl, C, tcl, etc.
- BS/MS in EE, CS, CSE (or similar)