
SoC Physical Design Engineer, STA/Timing
- Beaverton, OR
- Permanent
- Full-time
- Minimum BS and 10+ years of relevant industry experience.
- Strong programming skills with TCL.
- Experience with large design STA and/or Timing Closure.
- Experience with timing of large high-performance SoC designs in sub-micron technologies.
- Deep understanding of noise, crosstalk, OCV and other timing modeling effects.
- Knowledge of circuit modeling including timing models, worst-case timing corner selection, and SPICE simulation.
- Experience in ECO techniques and implementation.
- Experience with other scripting languages such as Perl or python.
- Good communicator who can accurately describe issues, propose solutions, and drive them through completion.